1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a half voltage generator for use in a semiconductor memory device.
2. Description of the Related Art
In a read operation of a semiconductor memory device, data stored in a memory cell is sensed and amplified by a sense amplifier (S/A) that is connected to a bitline (BL) and a complementary bitline (BLB), and externally provided. After the S/A's sense and amplification operations, the device precharges the BL and BLB to a predetermined level. The precharge operation is classified broadly into two methods. The first method is to precharge the BL to a voltage source VCC and the BLB to a ground voltage VSS. The second method is to precharge the BL and BLB to a half voltage source VCC or Half VCC. The first method is called a full voltage source precharge and the second method is called a half voltage source precharge. The full VCC precharge consumes more power than the half VCC precharge, thus most of semiconductor memory devices employ the half VCC precharge method. To execute the half VCC precharge method, a half voltage source (half VCC) generator is needed within the chip.
FIG. 1 shows a circuit diagram of a conventional half VCC generator. Referring to FIG. 1, the half VCC generator includes two MOS resistances MP0 and MN0, two diodes MN1 and MP1, a pull-up driver MN2, and a pull-down driver MP2. A voltage at a node NDA is set by a resistance ratio of the MOS resistances MP0 and MN0, and the drivers voltage of the node NDA is applied to each of gates of the pull-up and pull-down drivers MN2, MP2 through two diodes MP1 and MN1. The pull-up and pull-down drivers operate by a voltage level applied to each gate thereof to thus output a half voltage VBL. That is, a level of the outputted VBL is traced to a voltage level of the node NDA.
In FIG. 1, the VBL is commonly fed back to each of gates of the two MOS resistances MP0 and MN0. When a level of the VBL becomes a half level of the voltage source VCC and thus a size of transistors of the MOS resistances MP0 and MN0 is adjusted so that the voltage level of the NDA becomes the half VCC, a voltage by a threshold of respective diodes is applied to each of gates of the pull-up and pull-down drivers MN2 and MP2. To set the VBL, the size of the MOS transistors MP0 and MN0 is adjusted so that the voltage at NDA becomes half VCC. Once a level of the outputted VBL is deviated from the half VCC, resistance values of the two MOS resistances MP0 and MN0 are changed by a feedback operation, and thus a voltage level of the NDA is also changed. The changed voltage level changes a gate voltage of the pull-up and pull-down drivers MN2 and MP2, to thus stably maintain a level of the VBL of an output terminal as a level of the half VCC.
A tendency toward improved semiconductor technology and for a low-power memory, results in lowering VCC. The conventional half VCC generator, however, is limited by the two transistors MP0 and MN0 being used as the resistances. Transistors MP0 and MN0 might turn off as VCC is lower than a predetermined level. In other words, the two transistors MP0 and MN0 receive the half VCC as a gate voltage and this voltage is gradually lowered, resulting in one of the transistors turning off thereby improperly operating the voltage generator.
The half VCC generator shown in FIG. 1 has an advantage that the two drivers MN2 and MP2 do not turn on at the same time when a level of the half voltage is above a threshold voltage Vt of the transistor. Thus a standby current is small and a level of a determined half voltage can be maintained more precisely.
FIG. 2 shows another conventional half Vcc generator. Referring to FIG. 2, the voltage generator employs two differential amplifiers DA1 and DA2 to drive driver transistors. Thus, the voltage generator has a great driving capability as compared with the circuit of FIG. 1. Also the circuit of FIG. 2 has a low-voltage limitation of 1Vt+Vds_sat in comparison with that the circuit of FIG. 1, which has a low-voltage limitation of 2Vt. There is, therefore, an advantage that the circuit of FIG. 2 has a low limitation for the low-voltage and a high driving force, but a disadvantage that both transistors MP12 and MN12 turn “ON” at the same time. This causes a leakage current to flow that causes the output voltage at node NDB to oscillate.
The conventional half voltage source generators, therefore, might have a low driving capability, not be capable of a low-voltage operation, contain a leakage current flow, and cause oscillation at an output node. Accordingly, a need exists for an improved half voltage source generator.